This invention relates to a read only memory (ROM) using MOS transistors as memory cells.
A read only memory using MOS transistors can be proposed as is shown in FIG. 1A. The MOS transistors arranged in such pattern constitute a so-called "silicon gate type MOS IC". The cross sections of the MOS IC taken along line B--B, line C--C and line D--D are shown in FIGS. 1B, 1C and 1D, respectively.
The read only memory of FIGS. 1A to 1D comprises gate lines 1a, 1b, 1c, . . . , ROM output lines 2a, 2b, 2c, . . . , ground lines 3a, 3b, . . . , MOS transistors 4.sub.11, 4.sub.12, 4.sub.13, . . . , 4.sub.33, a P-type silicon substrate 5, N.sup.+ -type diffusion layers 6a, 6b, 6c, . . . , contacts 7a, 7b, 7c, . . . provided on the ROM output lines 2a, 2b, . . . , gate oxide films 8.sub.1a, 8.sub.1b, 8.sub.1c, . . . field oxide films 8.sub.2a, 8.sub.2b, 8.sub.2c, . . . On one major surface of the P-type silicon substrate 5 each ground line is juxtaposed with two gate lines. For example, the ground line 3a is juxtaposed with the gate lines 1b and 1c, and the ground line 3 b with the gate lines 1d and 1e. The ROM output lines 2a, 2b, . . . intersect with the gate lines 1a, 1b, . . . and the ground lines 3a, 3b, . . . The ground lines 3a, 3b, . . . are formed by N.sup.+ impurity diffusion. Thus the MOS transistors 4.sub.11, 4.sub.12, . . . are formed in the hatched areas in FIG. 1A, each constituted by adjacent ground line, N.sup.+ -type diffusion layer and gate line. The ground lines 3a, 3b, . . . constitute the sources of the MOS transistors 4.sub.11 to 4.sub.33, and the N.sup.+ -type diffusion layers 6a, 6b, . . . the drains thereof.
The ROM of FIGS. 1A to 1D is disadvantageous in that its 1-bit memory cell indicated by double dot-dash line occupies a relatively large areas. As commonly known, the contacts 7a, 7b, . . . must occupy an area 1a larger than necessary. Otherwise the yield of the IC products cannot be maintained above a certain level. It is also known that the IC density of ROMs of this type depends largely on the size of contacts. In the ROM of FIGS. 1A to 1D the contacts 7a, 7b, . . . arranged parallel to one another at regular intervals are extending in the lateral direction of the MOS IC. The MOS IC is therefore elongated in the lateral direction. Moreover, the contacts 7a, 7b, . . . are not so frequently used since each contact is located between only two MOS transistors which extend in the longitudinal direction of the MOS IC along the ROM output lines 2a, 2b, . . . For these reasons, the area S occupied by one 1-bit memory cell is: EQU S=l.times.m=20 .mu.m.times.17 .mu.m=340 .mu.m.sup.2.
340 .mu.m.sup.2 is an extremely large area for a 1-bit memory cell, and the MOS IC cannot have a large IC density.
The ROM of FIGS. 1A to 1D has such a circuit structure as illustrated in FIG. 2, wherein the same parts are denoted by the same reference numerals as used in FIGS. 1A to 1D.
Another ROM using MOS transistors can be proposed as is illustrated in FIGS. 3A, 3B and 3C. In this ROM the output lines act also as ground lines. To read out data from a memory cell (i.e. MOS transistor) via a selected one of the output lines, a switching circuit is so operated as to connect to the ground the output line which is adjacent to the selected output line. The ROM comprises gate lines 1a, 1b, 1c, . . . , output lines 2a, 2b, 2c, . . . , memory cells 4.sub.11 to 4.sub.32, a P-type silicon substrate 5, gate oxide films 8.sub.1 and field oxide films 8.sub.2 . . . The ROM has such a circuit structure as shown in FIG. 4A. As illustrated in FIG. 4A, the switching among the output lines 2a, 2b, 2c, . . . is carried out by a switching circuit 11.
Another known ROM using MOS transistors is illustrated in FIG. 4B. This ROM is identical with the ROM shown in FIG. 3A with respect to ROM section 4. It is characterized in that four output lines 2a, 2b, 2c and 2d form one group and are so connected to the ROM section 4 as to obtain the outputs of the ROM section. Suppose the output line 2a connected to an MOS transistor 12a is selected. Then, an MOS transistor 12e connected to the output line 2b adjacent to the selected line 12a is driven at once by an output of a switching circuit such as one 11 shown in FIG. 4A. In this case the output line 2b acts as a ground line. When the output line 2d connected to an MOS transistor 12d, for example, is selected, an MOS transistor 12h connected to an output line 2e of the next group is driven immediately by an output of the switching circuit. In this case the output line 2e acts as a ground line. Since only one of the output lines of each group is selected at a time, one of the remaining output lines is used as a ground line.
Indeed the ROMs of FIGS. 4A and 4B have a little higher IC density than the ROM of FIGS. 1A to 1D. But their cost is inevitably high for their structures. That is, the gate lines 1a, 1b, 1c, . . . made by polysilicon extend in the lateral direction of the MOS IC, while the output lines (or diffusion layers) 2a, 2b, 2c, . . . extend in the longitudinal direction of the MOS IC. Between any two adjacent output lines a plurality of MOS transistors are formed. Apparently, the gate lines 1a, 1b, 1c, . . . which intersect with the N.sup.+ -type diffusion layers 2a, 2b, 2c, . . . make masks for forming the N.sup.+ -type diffusion layers 2a, 2b, 2c, . . . As a result, it becomes impossible to simultaneously achieve N.sup.+ impurity diffusion for forming the MOS transistors 4.sub.11 to 4.sub.33 and N.sup.+ impurity diffusion for forming the output lines 2a, 2b, 2c, . . . Thus, N.sup.+ impurity must diffused two times, first to form the MOS transistors and then to form the output lines. This increase of impurity diffusion processes is one of the causes for cost hike.